1. Field of the Invention
The embodiments of the invention generally relate to transistors, and more particularly, to a silicon on insulator (SOI) field effect transistor (FET) that includes source/drain regions that are shallower than the channel region.
2. Description of the Related Art
Conventional silicon-on-insulator (SOI) field effect transistors (FET) use a relatively thin layer of semiconducting material, e.g., Si, overlaying a layer of insulating material, e.g. a buried oxide or dielectric layer. The relatively thin semiconductor layer is generally the area in which active devices, e.g., FETs, are fabricated. In high-performance SOI logic devices, the logic devices, i.e., FETs, are built within the relatively thin Si region of the SOI substrate to minimize source and drain capacitance.
Fully-depleted SOI FET devices can show large threshold voltage variations. The threshold voltage variations are effected by SOI thickness as well as the channel length variations that are a result of conventional device fabrication techniques.
SOI FETs are often distinguished as partially depleted (PD) when the silicon film is thicker than the maximum gate depletion region thickness, and fully depleted (FD) when the silicon film is thin enough that the entire film is depleted before the threshold voltage condition is reached. Because of current technology scaling trends in reducing the SOI thickness, partially-depleted SOI devices are being pushed closer and closer to the fully-depleted mode.
A well-designed halo implant can create devices such that the total channel doping concentration is higher in short channel devices resulting in a more useful threshold voltage when the drain voltage is high. Therefore, devices can be operated at much shorter channel lengths. This method however is difficult to extend further because the junction leakage current may be too high because of the high halo doping concentration and the doping fluctuation effect could dominate the threshold variations in short-channel length devices.
Improving a parameter such as threshold voltage (Vt) can result in degradation of various other parameters such as resistance (Rseries) or junction capacitance (Cj), for example. Many examples are evident where attempts have been made to minimize the tradeoffs between the various parameters of a high-speed semiconductor device.
For example, U.S. Patent Application Number 2006/0001095 A1, incorporated herein by reference, teaches a method of creating ultrathin body, fully-depleted SOI MOSFETs wherein the SOI thickness changes with gate-length variations; thus, minimizing threshold voltage variations that are typically caused by SOI thickness. The method uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. Also, U.S. Patent Application Number 20050110079 A1, incorporated herein by reference, teaches a method of forming a double gate FET.
Further, U.S. Patent Application Number 2005/0189589 A1, incorporated herein by reference, teaches a hybrid bulk/SOI FET where the transistor is formed at a surface of a layer of semiconductor material and comprises a gate structure formed on the surface of the layer of semiconductor material and a discontinuous film of material within the layer of semiconductor material aligned with the gate structure of the transistor.
U.S. Pat. No. 5,376,578 A, incorporated herein by reference, teaches a method of forming a FET in which the source, drain and isolation regions are all raised above the surface of the single crystal silicon which includes the steps of depositing a blanket gate stack including the gate oxide and a set of gate layers and then depositing isolation member apertures etched in the gate stack using the gate oxide as an etch stop.